1. Field of the Invention
The present invention generally relates to board-on-chip and chip-on-board ball grid array, including fine ball grid array, semiconductor chip packages. The present invention more particularly relates to constructing ball grid array semiconductor chip packages that are particularly suitable for being burned-in and tested in a more efficient and cost-effective manner. The subject invention further provides stackable ball grid array semiconductor chip packages which may be used to form highly dense, low-profile microelectronic components in which the semiconductor chip, or device, is better protected.
2. State of the Art
Ball grid array (BGA), including fine ball grid array (FBGA), semiconductor device packages are well known in the art. For convenience, a representative prior art BGA package is shown in drawing FIGS. 1 through 3. BGA chip packages, such as exemplary chip package 10, often comprise a substrate 12, such as a printed circuit board, having an elongated aperture 14 extending through the middle thereof. A semiconductor die or device 16, such as a dynamic random access memory (DRAM) device for example, is mounted on the opposite or bottom side of the substrate which is not viewable in drawing FIG. 1. Semiconductor die or device 16 most often will have a plurality of bond pads 20 in single column or multiple columns on an active surface 18 of semiconductor die 16. The active surface 18 of semiconductor die 16 is shown facing upward and can be viewed through aperture 14 in drawing FIG. 1. Substrate 12 is provided with an upwardly facing top surface 22, as shown in drawing FIG. 1, having a plurality of contact or bond pads 24 located along the periphery of aperture 14. Circuit traces 26 located on or within substrate 12 serve to electrically connect bond pads 20 to respective electrically conductive, connective elements such as solder balls 28. The electrically conductive elements typically comprise solder balls in electrical communication with and attached to a contact pad (not shown in FIGS. 1–3), or can merely be a solder ball placed directly upon, or in electrical communication with, the termination point of a selected circuit trace 26. Gold-filled or other conductive metal-based solder balls are frequently used. Alternatively, conductive balls made of a conductive-filled epoxy material having specifically preselected conductive qualities are also frequently used. The conductive elements or balls are arranged in a grid array pattern wherein the conductive elements or solder balls 28 are of a preselected size or sizes and are spaced from each other at one or more preselected distances, or pitches. Hence, the term “fine ball grid array” (FBGA) merely refers to a particular ball grid array pattern having what are considered to be relatively small conductive elements or solder balls 28 being spaced at very small distances from each other resulting in dimensionally small spacings or pitch. As generally used herein, the term “ball grid array” (BGA) encompasses fine ball grid arrays (FBGA) as well as ball grid arrays. Typical solder ball sizes can be approximately 0.6 mm or less and the solder balls may have a spacing or pitch of approximately 0.80 mm or less. However, the present invention is not limited with respect to a particular solder ball diameter or pitch.
Contact or bond pads 20 on active surface 18 of semiconductor die 16 are electrically and, to an extent mechanically, attached to respective contact pads 24 located on active surface 18 of substrate 12 by way of respective bond wires 30 by wire bonding methods known and practiced within the art.
Referring now to drawing FIGS. 2 and 3, which are cross-sectional views taken along line 2/3—2/3 as shown in drawing FIG. 1, bottom side or surface 32 of substrate 12 and nonactive side 36 of semiconductor die 16 are denoted. Semiconductor die or device 16 is attached to bottom side 32 of substrate 12 by any suitable adhesive 34. Illustrated in drawing FIG. 3 is an encapsulant 38 disposed over contact pads 24, bond wires 30, and bond pads 20 so as to protect and secure the somewhat fragile bond wires and bond sites from environmentally induced corrosion or other physical harm during immediately subsequent processing, storage, shipment, further processing, and ultimately during end use.
For quality control purposes, as well as manufacturing efficiency, it is standard practice to burn-in and electrically test semiconductor chip packages, such as representative prior art chip package 10, prior to installing the packages on the next-higher level of assembly, such as upon a dual in-line memory module (DIMM). Those chip packages that do not successfully undergo burn-in and testing are either reworked and retested or scrapped in accordance with economic feasibilities of the particular chip package being manufactured. In order to perform such pre-installation burn-in and testing, that is, intentionally subjecting the packages to elevated voltages and temperatures and then running preliminary, and perhaps diagnostic, tests on BGA chip packages such as BGA chip package 10, the chip packages must be mounted in specifically designed test tooling. A simplified illustration of representative test tooling 40 is shown in drawing FIG. 4. Generally, each BGA chip package 10 is placed in chip-receiving cell 44 of tray or holder 42. Chip package 10 usually has, but may not have, encapsulant 38 disposed thereon at the time of burn-in and testing. Upon chip package 10 being properly seated in tray 42, probe head 46 is moved toward chip package 10 in the direction of the arrow so as to engage each probe 48 with a corresponding conductive element such as solder ball 28. Upon BGA chip package 10 being burned-in and tested, probe head 46 is withdrawn from the chip package and the chip package is removed from test tray or holder 42 and forwarded on for further processing depending on the test results.
Because there are typically a large number of such solder balls to be contacted by a like number of probes for each chip package which must be arranged in a precise array or pattern in order to make electrical contact with the underlying solder balls, the test tooling is quite expensive, as well as time consuming, to construct. The time and expense factors of providing specific test tooling for each type of BGA chip having a wide variety of ball grid array patterns is compounded when the particular BGA chips to be burned-in and tested are of the fine ball grid array variety wherein the balls and spacing are quite small, thereby making the construction of the chip package test tooling even more time consuming and expensive. Furthermore, the specific test tooling to be devised must not only accommodate, burn-in, and test a single chip package, but must also be able to simultaneously accommodate, burn-in, and test a significant number of other chip packages, which may or may not have been segmented from a common substrate and are usually positioned and accompanied by respective cells of test tooling so that production quantities can be produced economically. Thus, it can be appreciated that the time and expense of constructing BGA chip package test tooling which, by necessity, has a multiplicity of probes specifically sized and arranged in patterns which must exactly correspond to the respective solder ball array being tested, are significant hindrances to quickly introducing BGA chip packages and, in particular, FBGA chip packages having new and different solder ball array patterns to the very competitive semiconductor chip marketplace. Furthermore, the test probes of the test tooling must be designed not to unduly damage the solder balls which will ultimately be used to electrically and mechanically connect the chip package to the next level of assembly by solder ball attachment methods used within the art.
U.S. Pat. No. 5,977,784, issued to Pai on Nov. 2, 1999, and related U.S. Pat. No. 5,831,444, issued to Pai on Nov. 3, 1998, are directed toward a method and apparatus for testing BGA chip packages wherein chip packages are placed within a self-centering test housing wherein contacts of the chip package are brought into contact with respective matching contact pads in order to burn-in and test the chip package. However, the testing apparatus of Pai must be provided with matching test contacts having the same array or pattern of the contact pads of the chip package to be tested in order to properly test the chip package. Thus, the substrate in which the test pads are located must be specifically manufactured to match the specific grid array of the chip package to be tested, giving rise to previously discussed unwanted new product lead times and expenses.
U.S. Pat. No. 6,018,249 issued to Akram et al. on Jan. 25, 2000, and assigned to the assignee of the present invention, provides a further example of a testing system for the testing of chip packages having external contacts or bumps arranged in a BGA or FBGA pattern. Notwithstanding the desirable features of the Akram et al. patent, the disclosed testing system includes matching contacts being provided and suitably positioned for respectively connecting with a correspondingly positioned external contact or bump on the chip package to be tested.
U.S. Pat. No. 5,677,566 issued to King et al. on Oct. 14, 1997, and assigned to the assignee of the present invention, is directed toward overcoming a problem in the industry wherein bare chips are continuously made increasingly smaller yet the chip-molded, plastic resin encapsulated, package-to-external circuit electrical connection typically remains at a previous, industry-set size and configuration when chips were larger. The semiconductor chip package taught by the King et al. U.S. Pat. No. 5,677,566 patent is provided with a lead frame having leads that generally originate near the center of the package and extend generally laterally outwardly over the chip toward and, if desired, beyond the periphery of the encapsulating material which generally defines the chip package. The innermost region of each conductive lead is wire bonded to a respective bond pad located on the active surface of the chip. The conductive leads near the periphery of the chip are exposed for accommodating a solder ball or other conductive element on the upper surface of the package, which is ultimately to be mounted on a printed circuit board in accordance with previous industry standards. The laterally protruding outer end portions of the individual conductive leads facilitate testing of the chip as the ends can be contacted with presently used testing equipment. After testing, the protruding ends can be trimmed flush with the exterior of the plastic resin package. Alternatively, the laterally protruding outer end portions of the conductive leads may be trimmed prior to encapsulating the entire chip package with plastic resin. Although suitable for many applications, providing the separate lead frame and fully encapsulating the chip package of King et al. may unnecessarily add to the complexity and cost of manufacturing chips to be used in other applications.
U.S. Pat. No. 5,731,709, issued to Pastore et al. on Mar. 24, 1998, discloses a ball grid array semiconductor device and apparatus for testing the device. In particular, Pastore et al. disclose a chip mounted on the top surface of a substrate which has a plurality of conductive castellations positioned around the periphery of the substrate serving as redundant electrical connections that are in communication with respective bond pads on the semiconductor chip. The conductive castellations, which are disclosed as being conductive vias that have been formed in the substrate which are subsequently trimmed to define the periphery of the substrate, thereby cutting the conductive vias in half, are engaged by specifically designed test apparatus to avoid directly contacting solder balls located on the top surface of the substrate. The test apparatus includes a test socket designed to accommodate the semiconductor device having contact members to make contact with the conductive castellations located about the periphery. The disclosed test apparatus appears to have been specifically designed to accommodate the disclosed semiconductor device. Thus, it would appear that added monetary costs would be incurred upon constructing and incorporating such test apparatus, or at least the disclosed test socket, into a production line.
In addition to the semiconductor packaging industry being driven to increase the number of solder balls or conductive contacts that is to be included within a BGA chip package of a given surface area, the industry is also being driven to reduce the overall height or profile of packaged semiconductor chips so that components and modules incorporating such chips can be made yet smaller and more compact. Thus, the industry is seeking ways in which BGA chip packages can be constructed so as to further reduce their individual height. Furthermore, the industry is seeking ways in which BGA chip packages may be stacked one upon another, which are, in turn, attached to a substrate or board to provide modules, such as dual in-line memory modules, of ever slimmer profiles.
An example of a lead chip design in a BGA package is shown in U.S. Pat. No. 5,668,405, issued to Yamashita on Sep. 16, 1997. The Yamashita patent discloses a semiconductor device that has a lead frame attached to the semiconductor chip. Through-holes are provided in a base film that allows solder bumps to connect via the lead frame to the semiconductor device. The Yamashita patent requires several steps of attaching the semiconductor device to the lead frame, then providing sealing resin, and then adding a base film and forming through-holes in the base film. A cover resin is added before solder bumps are added in the through-holes to connect to the lead frame. Thus, the resulting structure lacks the ability to stack devices one on top of another and further requires special test tooling be provided to match the particular grid pattern of the solder bumps.
U.S. Pat. No. 5,677,566, issued to King et al. on Oct. 14, 1997, referenced earlier herein, discloses a semiconductor chip package that includes discrete conductive leads with electrical contact bond pads on a semiconductor chip. The lead assembly is encapsulated with a typical encapsulating material and the solder balls or conductive elements are formed to protrude through the encapsulating material to contact the conductive leads and make contact with an external circuit. Although the semiconductor chip has the leads wire bonded to bond pads located in the center of the die, thereby allowing the conductive leads to be more readily protected upon being encapsulated by the encapsulating material, the chip package construction of the King et al. patent lacks the ability to be stacked one upon another.
With respect to stacking semiconductor chip packages, there are various methods of stacking semiconductor devices in three-dimensional integrated circuit packages known within the art. One such design is disclosed in U.S. Pat. No. 5,625,221, issued to Kim et al. on Apr. 29, 1997. The Kim et al. patent discloses a semiconductor package assembly that has recessed edge portions which extend along at least one edge portion of the assembly. An upper surface lead is exposed therefrom and a top recess portion is disposed on a top surface of the assembly. A bottom recess portion is disposed on the bottom surface of the assembly, such that when the assembly is used in fabricating a stacked integrated circuit module, the bottom recess portion accommodates leads belonging to an upper semiconductor assembly to provide electrical interconnection therebetween. Unfortunately, the assembly requires long lead wires from the semiconductor chip to the outer edges of the assembly. These lead wires add harmful inductance and unnecessary signal delay and can form a weak link in the electrical interconnection between the semiconductor chip and the outer edges. Further, the device profile is a sum of the height of the semiconductor chip, the printed circuit board to which it is bonded, the conductive elements, such as the solder balls, and the encapsulant that must cover the chip and any wire bonds used to connect the chip to the printed circuit board. So, reducing the overall profile is difficult because of the geometries required in having the lead pads on the semiconductor chip along the outer periphery with extended lead wires reaching from the chip to the outer edges of the assembly.
It can be appreciated that one of the favorable attributes of BGA chip packages is that the total height or overall thickness of the chip package is quite thin compared to other chip packages. Thus, BGA chip packages lend themselves to be especially suitable for incorporation within memory modules such as SDRAM modules and, in particular, dual in-line memory modules (DIMM).
Accordingly, what is needed within the art is a ball grid array chip package that can be easily burned-in and tested by existing test tooling. Another need within the art is for low-profile ball grid array chip packages that can be stacked so as to have a minimum amount of stack height to allow the production of low-profile dual in-line memory modules, for example. Such low-profile stackable packages would ideally have a lower profile than otherwise provided in the prior art and would ideally be producible with as few production steps as is feasible, yet provide adequate protection of the semiconductor chip during shipping and handling.